In complementary metal oxide silicon (CMOS) technology, the gate electrodes of n-channel and p-channel field effect transistors (FET) are interconnected. Thus, for a given applied voltage, one of the two devices will always be off. Such an arrangement provides a great power savings as compared to NMOS (i.e., solely n-channel FET) technology, wherein unnecessary current paths to ground abound.
In some CMOS circuits, it is also necessary to interconnect one of the n-type source/drain diffusion regions to one of the p-type source/drain diffusion regions. An example of such a circuit is the conventional six device static random access memory (SRAM) cell shown in FIG. 1 (Prior Art). In FIG. 1, the p-channel transistors are indicated by the boxes having a line through them and the n-channel transistors are indicated by the empty boxes. N-channel transistors 10 and 12 serve to access the memory cell defined by the four device latch comprised of n-channel devices 14 and 18 and p-channel devices 16 and 20. Of interest is the interconnection at N1 between the n-channel drain diffusion of transistor 14 and the p-channel drain diffusion of transistor 16, as well as the interconnection at N2 between the n-type drain diffusion of transistor 18 and the p-type drain diffusion of transistor 20.
Conventionally, these diffusion interconnections would be accomplished by depositing a layer of metal coupled to the diffusion regions in question through vias formed in a passivation layer. Examples of such interconnections are shown in FIGS. 1 and 2 of U.S. Pat. No. 4,661,202, entitled "Method of Manufacturing Semiconductor Device," issued Apr. 28, 1987, to Ochii and assigned to Toshiba. This patent also shows a trench filled with dielectric material for isolating the n-channel and p-channel devices from one another.
However, this conventional interconnect method presents disadvantages when applied to a circuit such as the SRAM cell of FIG. 1. Here, the circuit must be designed to maximize density. If we use the prior art metal interconnect techniques, the metal layer must provide (a) the interconnect between the diffusion regions at nodes N1 and N2; (b) the interconnect between node N1 and the gates of devices 18 and 20; (c) the interconnect between node N2 and the gates of devices 14 and 16, (d) the metal bit lines; and (e) the supply voltage contacts for VH and VG. It has been found by layout modelling that a metal layer cannot be defined to simultaneously meet all of the above interconnect requirements without substantially degrading the density of the memory cell.
In considering which of these interconnect functions should be borne by another conductive structure, it would be advantageous to use a structure that is on the same topological level as the structures to be interconnected. For example, the CMOS gate electrodes are typically interconnected by the same polysilicon layer that defines the gates. Since the interconnect functions (b)-(e) above necessitate an interconnection between a structure at one topological level to a structure of another topological level, it would be advantageous to meet interconnect requirement (a) utilizing a conductive structure at the same topological level (i.e., beneath the substrate surface) as the diffusion regions. The diffusion regions must be interconnected in a manner that does not affect the latchup prevention normally provided by an intervening isolation structure (see e.g., the Ochii patent cited above). If the diffusion regions are coupled together by simply incorporating a doped silicon region, unacceptable source/drain to substrate or n-well connections result.
Thus, a need has developed in the art for a structure that interconnects n-type diffusion regions and p-type diffusion regions without degrading circuit performance.